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For the Inventor, By the Inventor

Mountain View, CA, United States of America

Synopsys, Inc.


USPTO Granted Patents = 2,503



Trademarks = 50

Forward Citations = 20,896

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2,423 inventors (with patents filed for the assignee):

goldMedal Victor Moroz (147 out of 150 patents)

silverMedal Kenneth S McElvain (71 out of 106 patents)

bronzeMedal Jamil Kawa (66 out of 66 patents)

4.  Lawrence S Melvin, Iii (47 out of 47 patents)

5.  Mahesh A Iyer (43 out of 106 patents)

6.  Rohit Kapur (41 out of 41 patents)

7.  Xi-Wei Lin (37 out of 71 patents)

8.  Christophe Pierrat (35 out of 182 patents)

9.  Dipankar Pramanik (34 out of 125 patents)

10.  Deepak Dattatraya Sherlekar (32 out of 36 patents)

11.  Charles C Chiang (31 out of 31 patents)

12.  Peter Wohl (28 out of 31 patents)

13.  Andrew Edward Horch (28 out of 94 patents)

14.  John Theodore Stonick (28 out of 29 patents)

15.  Emil I Gizdarski (25 out of 25 patents)


Core Competencies:
Through-Silicon Vias
Machine Learning
Circuit Design
Analog Circuit Testing
Mask Synthesis
Power Supply Resistance
Functional Verification
Integrated Circuit Security
Low-Power Control Loops
High-Speed Interconnects
Static Timing Analysis
Safety Mechanisms

2,503 patents:

1. 12532544 - Split N-well cells having a merged N-well design (2026-01-20),
2. 12530518 - Length compensating waveguide for an optical circuit (2026-01-20),
3. 12530515 - Maximizing detectable defect coverage of analog circuits in integrated circuit design (2026-01-20),
4. 12530513 - Intelligent replay of simulation on modified constraint random testbench (2026-01-20),
5. 12530257 - Dual-error correcting code (ECC) for metadata in memory system (2026-01-20),
6. 12524594 - Mixed diffusion break for cell design (2026-01-13),
7. 12524591 - Library scaling for circuit design analysis (2026-01-13),
8. 12524589 - Functional safety mechanisms for input/output (IO) cells (2026-01-13),
9. 12518077 - Simultaneous multi-scenario static noise analysis (2026-01-06),
10. 12517850 - Interposer routing for universal chiplet interconnect express™ channels by partitioning into subchannels (2026-01-06),
11. 12512151 - Memory with hybrid write assist scheme (2025-12-30),
12. 12511237 - Memory address caching for neural networks (2025-12-30),
13. 12510592 - Dynamically configurable system-on-chip network (2025-12-30),
14. 12505273 - Dividing a chip design flow into sub-steps using machine learning (2025-12-23),
15. 12505271 - Event-driven tracing in static timing analysis of digital circuit designs (2025-12-23),
Synopsys, Inc. is an American electronic design automation company that focuses on providing software and intellectual property products used to design and test integrated circuits. Their solutions enable the development of chips and systems that power various electronic devices, from smartphones to televisions. With a wide range of innovative products, Synopsys helps customers optimize designs, reduce risks, and accelerate time-to-market for semiconductor and electronic systems. Their comprehensive tools and services cover the entire chip design and verification process, ensuring high-quality results and efficient workflows.
This text is generated by artificial intelligence and may not be accurate.

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USPTO Data Jan 1 1976 - Jan 20 2026

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2,503 Patents

#4 in Mountain View, CA

#48 in California

#185 in US

#378 in the World

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Mountain View, CA, United States of America

Synopsys, Inc.

Forward Citations = 20,896

2,423 inventors:

goldMedal Victor Moroz (147 out of 150 patents)

silverMedal Kenneth S McElvain (71 out of 106 patents)

bronzeMedal Jamil Kawa (66 out of 66 patents)

4.  Lawrence S Melvin, Iii (47 out of 47 patents)

5.  Mahesh A Iyer (43 out of 106 patents)

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