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For the Inventor, By the Inventor

Mountain View, CA, United States of America

Deepak Dattatraya Sherlekar

This inventor holds 36 USPTO granted patents and 4 published patent applications and 3 EPO patents, primarily in Integrated Circuit Design. Top assignees: Synopsys, Inc., Virage Logic Corporation. Active years: 2003-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Deepak Dattatraya Sherlekar. Retrieved from https://idiyas.com/inventor/deepak-dattatraya-sherlekar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 36 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.5

ph-index = 12

Forward Citations = 544(Granted Patents)


Location History:

  • Mountain View, CA (US) (2022)
  • Cupertino, CA (US) (2003 - 2024)

Company Filing History:

goldMedal32 out of 2,595 
 
Synopsys, Inc.
 patents
silverMedal4 out of 99 
 
Virage Logic Corporation
 patents

Years Active: 2003-2026

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Areas of Expertise:
Integrated Circuit
FinFET Architecture
Power Efficiency
Cell Design
Multi-Bit Flip Flop
Custom-Tiled Placement
Power Routing
Transistor Size
Volatile Latch Circuit
Cell Libraries
Diffusion Break
Engineering Change Order
36 patents (USPTO):Explore Patents
1. 12524594 - Mixed diffusion break for cell design (2026-01-13),
2. 12248744 - Poly-bit cells (2025-03-11),
3. 12231125 - Power efficient retention flip flop circuit (2025-02-18),
4. 12086523 - Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries (2024-09-10),
5. 12079558 - On-the-fly multi-bit flip flop generation (2024-09-03),
6. 11847396 - Integrated circuit design using multi-bit combinational cells (2023-12-19),
7. 11837280 - CFET architecture for balancing logic library and SRAM bitcell (2023-12-05),
8. 11790150 - Placement and simulation of cell in proximity to cell with diffusion break (2023-10-17),
9. 11681848 - On-the-fly multi-bit flip flop generation (2023-06-20),
10. 11657205 - Construction, modeling, and mapping of multi-output cells (2023-05-23),
11. 11416661 - Automatic derivation of integrated circuit cell mapping rules in an engineering change order flow (2022-08-16),
12. 11403454 - Placement and simulation of cell in proximity to cell with diffusion break (2022-08-02),
13. 11328109 - Refining multi-bit flip flops mapping without explicit de-banking and re-banking (2022-05-10),
14. 10990722 - FinFET cell architecture with insulator structure (2021-04-27),
15. 10205440 - Retention flip-flop circuits for low power applications (2019-02-12),

Title: The Innovative Mind of Deepak Dattatraya Sherlekar

Introduction: Deepak Dattatraya Sherlekar is a pioneering inventor based in Mountain View, CA. His inventive spirit and dedication to technological advancements have made him a prominent figure in the world of innovation.

Latest Patents: Deepak Dattatraya Sherlekar holds several patents in various fields, including artificial intelligence, renewable energy, and medical devices. His recent patents showcase his commitment to creating solutions that have a positive impact on society.

Career Highlights: With a background in engineering and a passion for problem-solving, Deepak Dattatraya Sherlekar has had a successful career marked by groundbreaking inventions. His ability to think outside the box and his relentless drive to innovate have led to significant contributions in the tech industry.

Collaborations: Throughout his career, Deepak Dattatraya Sherlekar has collaborated with leading tech companies, research institutions, and universities to bring his inventions to life. His collaborative efforts have resulted in the development of cutting-edge technologies that have the potential to shape the future.

Conclusion: Deepak Dattatraya Sherlekar's innovative spirit and dedication to creating impactful solutions have solidified his reputation as a visionary inventor. His contributions to the world of technology continue to inspire and pave the way for future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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