The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Jun. 12, 2023
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Sai Yaswanth Divvela, Andhra Pradesh, IN;

Amit Verma, Telangana, IN;

Basannagouda Reddy, San Jose, CA (US);

Deepak D. Sherlekar, Cupertino, CA (US);

Assignee:

SYNOPSYS, INC., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 3/037 (2013.01); H03K 3/012 (2013.01);
Abstract

A circuit includes: a first latch; a second latch coupled to the first latch; and a third latch coupled to the second latch at an input terminal of the second latch, wherein the third latch includes: a first inverter and a second inverter, the first inverter being coupled between the input terminal of the second latch and an input terminal of the second inverter and the second inverter being coupled between an output terminal of the first inverter and an input terminal of the first inverter; a first switch connecting the first inverter to a first voltage source; a second switch connecting the first inverter to ground voltage; a third switch connecting the second inverter to the first voltage source; a fourth switch connecting the second inverter to the ground voltage; and a fifth switch connecting the second latch and the first inverter.


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