The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Jul. 30, 2020
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Deepak Dattatraya Sherlekar, Mountain View, CA (US);

Mohammad Ziaullah Khan, Mountain View, CA (US);

Channakeshav Ananth, Bangalore, IN;

Muniraj Ramamurthy, Mountain View, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract

Refining multi-bit flip flops mapping without explicit de-banking and re-banking is provided by identifying a set of equivalent flops in a layout, that include a first flop having a first logic routing and a first location in the layout and a second flop having a second logic routing and a second location in the layout; and remapping the first logic of the first flop from the first location to the second location and the second logic of the second flop from the second location to the first location.


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