The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Sep. 27, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Deepak Dattatraya Sherlekar, Cupertino, CA (US);

Mohammad Ziaullah Khan, Folsom, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/3315 (2020.01); G06F 119/12 (2020.01); G06F 111/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/3315 (2020.01); G06F 2111/20 (2020.01); G06F 2119/12 (2020.01);
Abstract

A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second outputs of the cell in the compiled circuit design replace a plurality of outputs of the plurality of circuit elements.


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