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For the Inventor, By the Inventor

Fremont, CA, United States of America

Xi-Wei Lin

This inventor holds 72 USPTO granted patents and 9 published patent applications, primarily in Integrated Circuit Design (CPC class H01L). Top assignees: Synopsys, Inc., Vlsi Technology, Inc., Koninklijke Philips Corporation N.v.. Active years: 1998-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Xi-Wei Lin. Retrieved from https://idiyas.com/inventor/xi-wei-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 72 

% Patents Active = 94.4

Average Co-Inventor Count = 1.9

ph-index = 15

Forward Citations = 769(Granted Patents)

Forward Citations (Not Self Cited) = 738(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Freemont, CA (US) (2001)
  • Fremont, CA (US) (1998 - 2024)

Company Filing History:

goldMedal38 out of 2,595 
 
Synopsys, Inc.
 patents
silverMedal25 out of 1,083 
 
Vlsi Technology, Inc.
 patents
bronzeMedal5 out of 21,885 
 
Koninklijke Philips Corporation N.v.
 patents
4. 1 out of 5,322 
 
Nxp B.v.
 patents
5. 1 out of 838 
 
Philips Electronics North America Corporation
 patents
6. 1 out of 26 
 
Philips Semiconductors Inc.
 patents
7. 1 out of 5 
 
Vlsi Technologies, Inc.
 patents

Years Active: 1998-2026

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Areas of Expertise:
Integrated Circuits
CFET
Transistor Optimization
Epitaxial Growth
FinFET
Design Optimization
Circuit Simulation
High-Density Devices
Electrical Shorts
Power Delivery Network
Resistance Extraction
Process Variation
72 patents (USPTO):Explore Patents
1. 12581933 - Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network (2026-03-17),
2. 12453129 - Stacked nanosheet device for process and performance optimization (2025-10-21),
3. 12080608 - Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET) (2024-09-03),
4. 11984384 - Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network (2024-05-14),
5. 11915984 - Forming a wrap-around contact to connect a source or drain epitaxial growth of a complimentary field effect transistor (CFET) to a buried power rail (BPR) of the CFET (2024-02-27),
6. 11776816 - Fin patterning to reduce fin collapse and transistor leakage (2023-10-03),
7. 11742247 - Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET) (2023-08-29),
8. 11710634 - Fabrication technique for forming ultra-high density integrated circuit components (2023-07-25),
9. 10482212 - Automated resistance and capacitance extraction and netlist generation of logic cells (2019-11-19),
10. 10311200 - Pre-silicon design rule evaluation (2019-06-04),
11. 9547740 - Methods for fabricating high-density integrated circuit devices (2017-01-17),
12. 9471745 - Chip cross-section identification and rendering analysis (2016-10-18),
13. 9418189 - SRAM layouts (2016-08-16),
14. 9379018 - Increasing Ion/Ioff ratio in FinFETs and nano-wires (2016-06-28),
15. 9147027 - Chip cross-section identification and rendering during failure analysis (2015-09-29),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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