The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Aug. 23, 2019
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Hayk Grigoryan, Yerevan, AM;

Grigor Tshagharyan, Yerevan, AM;

Gurgen Harutyunyan, Yerevan, AM;

Samvel Shoukourian, Yerevan, AM;

Yervant Zorian, Mountain View, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 29/18 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1004 (2013.01); G06F 11/102 (2013.01); G11C 29/18 (2013.01); G11C 2029/1802 (2013.01);
Abstract

A system including a user interface, a memory, and a processor configured to perform operations including receiving memory scrambling information including address scrambling information and data scrambling information, and associating one or more address bus bits of a plurality of address bus bits with an address grouping of a plurality of address groupings based on the address scrambling information is disclosed. In an embodiment, the address grouping corresponds to at least one address segment of a plurality of address segments. The operations include determining an error correction code for the at least one address segment that includes one or more address check bits. The operations include generating a physical layout of memory components based on the memory scrambling information. The memory components include at least one of the plurality of address bus bits, and the one or more address check bits.


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