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For the Inventor, By the Inventor

Singapore, Singapore

Yeow Kheng Lim

This inventor holds 25 USPTO granted patents and 4 published patent applications, primarily in Integrated Circuit Design. Top assignees: Chartered Semiconductor Manufacturing Ltd (Corporation), Globalfoundries Singapore Pte. Ltd.. Active years: 2001-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yeow Kheng Lim. Retrieved from https://idiyas.com/inventor/yeow-kheng-lim

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25 

% Patents Active = 52.0

Average Co-Inventor Count = 5.0

ph-index = 8

Forward Citations = 205(Granted Patents)


Company Filing History:

goldMedal17 out of 962 
 
Chartered Semiconductor Manufacturing Ltd (Corporation)
 patents
silverMedal8 out of 1,060 
 
Globalfoundries Singapore Pte. Ltd.
 patents

Years Active: 2001-2016

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Areas of Expertise:
Integrated Circuit
Dual Damascene
TSV Processing
Low-k Dielectrics
Copper Interconnect
Silicon-On-Insulator
MIM Capacitors
Power Supply Integration
Metal Silicide
Crack-Arresting Structure
Aluminum Wiring
Reliability Enhancement
25 patents (USPTO):Explore Patents
1. 9318378 - Slot designs in wide metal lines (2016-04-19),
2. 8957523 - Dielectric posts in metal layers (2015-02-17),
3. 8860185 - Crack-arresting structure for through-silicon vias (2014-10-14),
4. 8766454 - Integrated circuit with self-aligned line and via (2014-07-01),
5. 8759947 - Back-side MOM/MIM devices (2014-06-24),
6. 8716856 - Device with integrated power supply (2014-05-06),
7. 8466062 - TSV backside processing using copper damascene interconnect technology (2013-06-18),
8. 8358007 - Integrated circuit system employing low-k dielectrics and method of manufacture thereof (2013-01-22),
9. 7790617 - Formation of metal silicide layer over copper interconnect for reliability enhancement (2010-09-07),
10. 7372156 - Method to fabricate aligned dual damascene openings (2008-05-13),
11. 7253097 - Integrated circuit system using dual damascene process (2007-08-07),
12. 7119010 - Integrated circuit with self-aligned line and via and manufacturing method therefor (2006-10-10),
13. 6967156 - Method to fabricate aligned dual damascene openings (2005-11-22),
14. 6849928 - Dual silicon-on-insulator device wafer die (2005-02-01),
15. 6780691 - Method to fabricate elevated source/drain transistor with large area for silicidation (2004-08-24),

Title: Yeow Kheng Lim - Pioneering Inventor from Singapore

Introduction: Yeow Kheng Lim is a renowned inventor hailing from Singapore, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Yeow Kheng Lim holds several patents in various technological domains, including artificial intelligence, renewable energy, and biotechnology.

Career Highlights: With a career spanning over two decades, Yeow Kheng Lim has worked with leading tech companies and research institutions, spearheading projects that have led to significant advancements in the industry.

Collaborations: Throughout his career, Yeow Kheng Lim has collaborated with top researchers, scientists, and engineers from around the world, fostering a culture of innovation and excellence.

Conclusion: Yeow Kheng Lim's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and researchers worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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