The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2007
Filed:
Jun. 30, 2005
Yeow Kheng Lim, Singapore, SG;
Chim Seng Seet, Singapore, SG;
Tae Jong Lee, Singapore, SG;
Liang-choo Hsia, Singapore, SG;
Kin Leong Pey, Singapore, SG;
Yeow Kheng Lim, Singapore, SG;
Chim Seng Seet, Singapore, SG;
Tae Jong Lee, Singapore, SG;
Liang-Choo Hsia, Singapore, SG;
Kin Leong Pey, Singapore, SG;
Chartered Semiconductor Manufacturing, Ltd., Singapore, SG;
Abstract
An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.