For the Inventor, By the Inventor

Enter inventor name

Yeh-Chi Hsu

USPTO Granted Patents = 9 (Patent Applications = 2)

Average Co-Inventor Count = 2.8

ph-index = 3

Forward Citations = 35(Granted Patents)

Location History:

Taipei Hsien, TW (2011 - 2014)
New Taipei, TW (2014 - 2020)

Company Filing History:

Via Technologies, Inc.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Alliance Semiconductor Co., Ltd.

Years Active: 2011-2020

Loading Chart...

9 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10756077 - Chip packaging method (2020-08-25),

2. 10504847 - Chip package structure and chip package structure array (2019-12-10),

3. 10204852 - Circuit substrate and semiconductor package structure (2019-02-12),

4. 9601425 - Circuit substrate and semiconductor package structure (2017-03-21),

5. 9418964 - Chip package structure (2016-08-16),

6. 8796848 - Circuit board and chip package structure (2014-08-05),

7. 8736079 - Pad structure, circuit carrier and integrated circuit chip (2014-05-27),

8. 8698325 - Integrated circuit package and physical layer interface arrangement (2014-04-15),

9. 7906377 - Fabrication method of circuit board (2011-03-15),

This text is generated by artificial intelligence and may not be accurate.

Please report any incorrect information to support@idiyas.com

Loading…