Yeh-Chi Hsu

This inventor holds 10 USPTO granted patents and 2 published patent applications. Top assignees: Via Technologies, Inc., Shanghai Zhaoxin Semiconductor Co., Ltd., Via Alliance Semiconductor Co., Ltd.. Active years: 2011-2025.

USPTO Granted Patents = 10 (Patent Applications = 2)

% Patents Active = 100.0

Average Co-Inventor Count = 2.8

ph-index = 3

Forward Citations = 36(Granted Patents)

Location History:

Taipei Hsien, TW (2011 - 2014)
New Taipei, TW (2014 - 2020)

Company Filing History:

6 out of 1,974

Via Technologies, Inc.

patents

2 out of 169

Shanghai Zhaoxin Semiconductor Co., Ltd.

patents

2 out of 283

Via Alliance Semiconductor Co., Ltd.

patents

Years Active: 2011-2025

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10 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12506060 - Package substrate, chip package and integrated circuit chip (2025-12-23),

2. 10756077 - Chip packaging method (2020-08-25),

3. 10504847 - Chip package structure and chip package structure array (2019-12-10),

4. 10204852 - Circuit substrate and semiconductor package structure (2019-02-12),

5. 9601425 - Circuit substrate and semiconductor package structure (2017-03-21),

6. 9418964 - Chip package structure (2016-08-16),

7. 8796848 - Circuit board and chip package structure (2014-08-05),

8. 8736079 - Pad structure, circuit carrier and integrated circuit chip (2014-05-27),

9. 8698325 - Integrated circuit package and physical layer interface arrangement (2014-04-15),

10. 7906377 - Fabrication method of circuit board (2011-03-15),

Title: Yeh-Chi Hsu: Innovator in Chip Packaging Technology

Introduction

Yeh-Chi Hsu is a prominent inventor based in Taipei, Taiwan. He has made significant contributions to the field of chip packaging technology, holding a total of 10 patents. His innovative work has advanced the design and functionality of integrated circuit chips and package substrates.

Latest Patents

Hsu's latest patents include a package substrate and a chip packaging method. The package substrate features a substrate surface with a chip region that includes circuit layers, conductive vias, and byte region rows. Each byte region is designed with pads located on the circuit layer closest to the substrate surface, enhancing connectivity and performance. The chip packaging method involves a series of steps where multiple first chips are placed on a carrier, and a second chip is connected through conductive pillars. This method ensures efficient encapsulation and redistribution of electrical connections.

Career Highlights

Throughout his career, Yeh-Chi Hsu has worked with notable companies such as Via Technologies, Inc. and Shanghai Zhaoxin Semiconductor Co., Ltd. His experience in these organizations has allowed him to refine his expertise in semiconductor technology and chip design.

Collaborations

Hsu has collaborated with talented individuals in the industry, including Wen-Yuan Chang and Wei-Cheng Chen. These partnerships have contributed to the development of innovative solutions in chip packaging.

Conclusion

Yeh-Chi Hsu's contributions to chip packaging technology have established him as a key figure in the field. His patents reflect a commitment to innovation and excellence in semiconductor design.