The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Dec. 14, 2017
Applicant:

Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

Wen-Yuan Chang, New Taipei, TW;

Yeh-Chi Hsu, New Taipei, TW;

Hsueh-Chung Shelton Lu, New Taipei, TW;

Wei-Cheng Chen, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 21/56 (2006.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/16 (2013.01); H01L 23/3128 (2013.01); H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/69 (2013.01); H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/18 (2013.01); H01L 2224/2499 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/69 (2013.01); H01L 2224/73209 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.


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