The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Mar. 16, 2022
Applicant:

Via Technologies, Inc., New Taipei, TW;

Inventors:

Wen-Yuan Chang, New Taipei, TW;

Yeh-Chi Hsu, New Taipei, TW;

Gao-Tian Lin, New Taipei, TW;

Assignee:

VIA Technologies, Inc., New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A package substrate has a substrate surface and a chip region on the substrate surface. The package substrate includes circuit layers, conductive vias, and byte region rows. The circuit layers are sequentially spaced below the substrate surface. Each conductive via is connected to at least two of the circuit layers. The byte region rows are arranged side by side sequentially from an edge of the chip region to a center of the chip region, and each byte region row includes byte regions arranged in a row. Each byte region includes pads located on the circuit layer closest to the substrate surface. The pads of the byte regions of the byte region row closer to the edge of the chip region extend from the chip region to an outside of the chip region through traces of the circuit layer closer to the substrate surface.


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