Via Technologies, Inc.

Via Alliance Semiconductor Co., Ltd.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Yeh-Chi Hsu

Wen-Yuan Chang

Wei-Cheng Chen

Chen-Yueh Kung

Wei-Chih Lai

Hsueh-Chung Shelton Lu

Yu-Kai Chen

Ying-Ni Lee

A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.

Chip packaging method

A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.

Chip package structure and chip package structure array

A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.

Circuit substrate and semiconductor package structure

The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface. A first through via plug passes through the core substrate. A first conductive line pattern and a second conductive line pattern adjacent to the first conductive line are disposed on the chip-side surface. A pad is disposed on the bump-side surface. The first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad. The first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type.

A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.

Chip package structure

A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.

Circuit board and chip package structure

A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

Pad structure, circuit carrier and integrated circuit chip

An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.

Integrated circuit package and physical layer interface arrangement

A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.

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Taipei, Taiwan

Yeh-Chi Hsu