The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2014

Filed:

Jan. 11, 2011
Applicants:

Wen-yuan Chang, Taipei Hsien, TW;

Wei-cheng Chen, Taipei Hsien, TW;

Yeh-chi Hsu, Taipei Hsien, TW;

Inventors:

Wen-Yuan Chang, Taipei Hsien, TW;

Wei-Cheng Chen, Taipei Hsien, TW;

Yeh-Chi Hsu, Taipei Hsien, TW;

Assignee:

Via Technologies, Inc., New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H05K 3/24 (2006.01); H01L 23/00 (2006.01); H05K 3/46 (2006.01); H05K 3/40 (2006.01); H05K 3/28 (2006.01);
U.S. Cl.
CPC ...
H05K 3/242 (2013.01); H01L 23/49822 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15174 (2013.01); H01L 2224/16225 (2013.01); H05K 2201/0352 (2013.01); H01L 2924/14 (2013.01); H05K 3/243 (2013.01); H05K 3/4602 (2013.01); H05K 3/4007 (2013.01); H05K 2201/09627 (2013.01); H01L 2924/01078 (2013.01); H05K 2201/09536 (2013.01); H01L 2224/81193 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/01046 (2013.01); H05K 2201/0367 (2013.01); H01L 2924/01029 (2013.01); H01L 2224/13099 (2013.01); H01L 2924/01079 (2013.01); H01L 23/49827 (2013.01); H01L 24/81 (2013.01); H01L 2224/81801 (2013.01); H05K 3/28 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/054 (2013.01); H01L 23/49811 (2013.01); H05K 2201/09481 (2013.01); H01L 24/16 (2013.01); H01L 2924/01033 (2013.01);
Abstract

A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.


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