Company Filing History:

10 out of 2,542

Cadence Design Systems, Inc.

Years Active: 2009-2022

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19 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11487930 - Pattern matching using anchors during integrated circuit verification (2022-11-01),

2. 10902176 - Detecting and displaying multi-patterning fix guidance (2021-01-26),

3. 10311195 - Incremental multi-patterning validation (2019-06-04),

4. 9384319 - Detecting and displaying multi-patterning fix guidance (2016-07-05),

5. 8718382 - Scalable pattern matching between a pattern clip and a pattern library (2014-05-06),

6. 8701056 - Automated repair method and system for double patterning conflicts (2014-04-15),

7. 8677301 - Method and system for model-based design and layout of an integrated circuit (2014-03-18),

8. 8645887 - Method and system for model-based design and layout of an integrated circuit (2014-02-04),

9. 8381152 - Method and system for model-based design and layout of an integrated circuit (2013-02-19),

10. 8358828 - Interpolation of irregular data in a finite-dimensional metric space in lithographic simulation (2013-01-22),

11. 8341571 - Pattern signature (2012-12-25),

12. 8291351 - Intelligent pattern signature based on lithography effects (2012-10-16),

13. 8151219 - System and method for multi-exposure pattern decomposition (2012-04-03),

14. 7966586 - Intelligent pattern signature based on lithography effects (2011-06-21),

15. 7934174 - Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout (2011-04-26),

Title: Innovations of Weiping Fang: A Leader in Integrated Circuit Verification

Introduction: Weiping Fang, based in Fremont, CA, is a prominent inventor with a notable portfolio of 19 patents. His contributions primarily focus on innovations in integrated circuit (IC) verification, which play a crucial role in enhancing design efficiency and accuracy within the semiconductor industry.

Latest Patents: Among his latest innovations are two significant patents. The first, titled "Pattern Matching Using Anchors During Integrated Circuit Verification," introduces a method for obtaining match time estimates associated with pattern anchors of various types for an IC pattern. This method not only generates revised match time estimates based on a target IC layout but also selects the pattern anchor associated with the shortest revised match time estimate. Furthermore, it facilitates the generation of target anchors and the search for the IC pattern using these anchors. The second patent, "Detecting and Displaying Multi-Patterning Fix Guidance," presents a computer-implemented method for validating designs. This innovative method generates a non-decomposable graph that represents the design and identifies guidance for conflicts in mask layouts, which are critical for ensuring design accuracy.

Career Highlights: Weiping Fang has made substantial contributions to the field of IC design and verification through his work at leading companies such as Cadence Design Systems, Inc. and Synopsys, Inc. His expertise has greatly influenced IC verification processes, setting new standards for efficiency and reliability.

Collaborations: Throughout his career, Weiping has collaborated with several talented professionals, including Junjiang Lei and Srini Doddi. These collaborations have fostered innovative solutions and advancements in IC verification technologies.

Conclusion: Weiping Fang stands out as a key innovator in the domain of integrated circuit verification. With his impressive array of patents and collaborations with industry experts, he continues to contribute to the advancement of technology that shapes the future of the semiconductor industry. His work not only enhances the accuracy of designs but also sets a benchmark for innovation and excellence in the field.

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