The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2013
Filed:
Jun. 05, 2008
Ya-chieh Lai, Sunnyvale, CA (US);
Frank E. Gennari, San Jose, CA (US);
Matthew Moskewicz, San Mateo, CA (US);
Srinivas Doddi, Fremont, CA (US);
Junjiang Lei, Bellevue, WA (US);
Weiping Fang, Fremont, CA (US);
Kuanghao Lay, Mountain View, CA (US);
Ya-Chieh Lai, Sunnyvale, CA (US);
Frank E. Gennari, San Jose, CA (US);
Matthew Moskewicz, San Mateo, CA (US);
Srinivas Doddi, Fremont, CA (US);
Junjiang Lei, Bellevue, WA (US);
Weiping Fang, Fremont, CA (US);
Kuanghao Lay, Mountain View, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.