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For the Inventor, By the Inventor

San Jose, CA, United States of America

Steev Wilcox

USPTO Granted Patents = 10

Average Co-Inventor Count = 4.1

ph-index = 3

Forward Citations = 30(Granted Patents)


Company Filing History:

goldMedal10 out of 2,542 
 
Cadence Design Systems, Inc.
 patents

Years Active: 2016-2023

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10 patents (USPTO):Explore Patents
1. 11748534 - System and method for glitch power estimation (2023-09-05),
2. 9817069 - Method and system for construction of a highly efficient and predictable sequential test decompression logic (2017-11-14),
3. 9817068 - Method and system for improving efficiency of sequential test compression using overscan (2017-11-14),
4. 9606179 - Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer (2017-03-28),
5. 9513335 - Method for using XOR trees for physically efficient scan compression and decompression logic (2016-12-06),
6. 9501590 - Systems and methods for testing integrated circuit designs (2016-11-22),
7. 9470756 - Method for using sequential decompression logic for VLSI test in a physically efficient construction (2016-10-18),
8. 9470755 - Method for dividing testable logic into a two-dimensional grid for physically efficient scan (2016-10-18),
9. 9470754 - Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization (2016-10-18),
10. 9465896 - Systems and methods for testing integrated circuit designs (2016-10-11),

Title: The Innovative Mind of Steev Wilcox: Revolutionizing Design Systems in San Jose, CA

Introduction: Steev Wilcox, a prolific inventor based in San Jose, CA, has made significant contributions to the field of electronic design with a remarkable portfolio of 10 patents. His groundbreaking work at Cadence Design Systems, Inc. showcases his ingenuity in pushing the boundaries of technology.

Latest Patents:

1. System and method for glitch power estimation: Wilcox's patent focuses on estimating glitch power during the emulation process by developing a probability-based model for inputs associated with an electronic design database. This method enhances accuracy and efficiency in power estimation, a critical aspect of electronic design.

2. Method and system for improving efficiency of sequential test compression using overscan: This patent by Wilcox demonstrates a method to enhance the efficiency of test compression in the ATPG process without requiring additional hardware. By overscanning and introducing more variables into the PRPG system, the testing process becomes more effective.

Career Highlights: Steev Wilcox's tenure at Cadence Design Systems, Inc. has been marked by pioneering research and innovation in electronic design. His relentless pursuit of excellence has led to the development of cutting-edge solutions that streamline processes and enhance performance in the industry.

Collaborations: Wilcox has collaborated closely with talented individuals in his field, including Paul Alexander Cunningham and Vivek Chickermane. These collaborations have been instrumental in driving forward-thinking projects and achieving remarkable results in the realm of electronic design.

Conclusion: Steev Wilcox stands as a trailblazer in the world of electronic design, with a proven track record of innovation and excellence. His patents and collaborations exemplify his dedication to advancing technology and shaping the future of electronic design systems.

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