The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Jun. 29, 2015
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Paul Alexander Cunningham, Mountain View, CA (US);

Steev Wilcox, San Jose, CA (US);

Vivek Chickermane, Slaterville Springs, NY (US);

Krishna Vijaya Chakravadhanula, Vestal, NY (US);

Brian Edward Foutz, Charlottesville, VA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3181 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G01R 31/319 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318544 (2013.01); G01R 31/31813 (2013.01); G01R 31/31921 (2013.01); G01R 31/318335 (2013.01); G01R 31/318547 (2013.01); G01R 31/3177 (2013.01); G01R 31/318536 (2013.01); G01R 31/318558 (2013.01);
Abstract

Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.


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