The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2016
Filed:
Jun. 12, 2015
Method for using sequential decompression logic for vlsi test in a physically efficient construction
Cadence Design Systems, Inc., San Jose, CA (US);
Steev Wilcox, San Jose, CA (US);
Brian Edward Foutz, Charlottesville, VA (US);
Krishna Vijaya Chakravadhanula, Vestal, NY (US);
Vivek Chickermane, Slaterville Springs, NY (US);
Paul Alexander Cunningham, Mountain View, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.