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For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

Srinivasan Dasasathyan

This inventor holds 22 USPTO granted patents, primarily in Circuit Design Optimization. Top assignee: Xilinx, Inc.. Active years: 2004-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Srinivasan Dasasathyan. Retrieved from https://idiyas.com/inventor/srinivasan-dasasathyan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22

% Patents Active = 95.5

Average Co-Inventor Count = 3.3

ph-index = 7

Forward Citations = 379(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (2004 - 2013)
  • Santa Clara, CA (US) (2008 - 2013)
  • Secunderabad, IN (2016 - 2023)

Company Filing History:

goldMedal22 out of 5,108 
 
Xilinx, Inc.
 patents

Years Active: 2004-2023

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Areas of Expertise:
Automated Timing Closure
Circuit Design
Data Bus Visualization
Integrated Circuits
Clock Placement
Performance Driven Legalization
FPGA Designs
Floorplanning
Net Delay Estimation
Resource Aware Partitioning
Programmable Logic Devices
Routability Based Placement
22 patents (USPTO):Explore Patents
1. 11714950 - Automated timing closure on circuit designs (2023-08-01),
2. 11586791 - Visualization of data buses in circuit designs (2023-02-21),
3. 11003826 - Automated analysis and optimization of circuit designs (2021-05-11),
4. 10867093 - System and method for an electronic design tool providing automated guidance and interface for circuit design processing (2020-12-15),
5. 9501604 - Testing critical paths of a circuit design (2016-11-22),
6. 8473881 - Multi-resource aware partitioning for integrated circuits (2013-06-25),
7. 8448122 - Implementing sub-circuits with predictable behavior within a circuit design (2013-05-21),
8. 8418115 - Routability based placement for multi-die integrated circuits (2013-04-09),
9. 8312405 - Method of placing input/output blocks on an integrated circuit device (2012-11-13),
10. 8230377 - Control set constraint driven force directed analytical placer for programmable integrated circuits (2012-07-24),
11. 8225262 - Method of and system for placing clock circuits in an integrated circuit (2012-07-17),
12. 8091060 - Clock domain partitioning of programmable integrated circuits (2012-01-03),
13. 7735039 - Methods of estimating net delays in tile-based PLD architectures (2010-06-08),
14. 7636876 - Cost-based performance driven legalization technique for placement in logic designs (2009-12-22),
15. 7392499 - Placement of input/output blocks of an electronic design in an integrated circuit (2008-06-24),

Title: The Innovative Journey of Srinivasan Dasasathyan

Introduction: Srinivasan Dasasathyan, a talented inventor based in Sunnyvale, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Srinivasan Dasasathyan holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his diverse expertise and forward-thinking approach.

Career Highlights: With a background in engineering and a passion for problem-solving, Srinivasan Dasasathyan has had a successful career working for leading tech companies, where he has spearheaded projects that have pushed the boundaries of innovation.

Collaborations: Throughout his career, Srinivasan Dasasathyan has collaborated with top researchers, engineers, and scientists in the industry, fostering a culture of creativity and excellence in all his projects.

Conclusion: Srinivasan Dasasathyan's relentless pursuit of innovation and his commitment to creating a positive impact through his inventions make him a true visionary in the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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