The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Mar. 20, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

John Blaine, Weybridge, GB;

Srinivasan Dasasathyan, Secunderabad, IN;

Meghraj Kalase, Hyderabad, IN;

Frederic Revenu, San Carlos, CA (US);

Veeresh Pratap Singh, Hyderabad, IN;

Satish Bachina, Hyderabad, IN;

Shail Bains, Hyderabad, IN;

Padmini Gopalakrishnan, Hyderabad, IN;

Sumit Nagpal, Hyderabad, IN;

Gaurav Dutt Sharma, Benares, IN;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/3323 (2020.01); G06F 30/30 (2020.01); G06F 30/10 (2020.01); G06F 30/20 (2020.01); G06F 30/00 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/30 (2020.01); G06F 30/00 (2020.01); G06F 30/10 (2020.01); G06F 30/20 (2020.01);
Abstract

Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.


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