The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2012

Filed:

Jan. 20, 2009
Applicants:

Victor Slonim, Broomfield, CO (US);

Rajat Aggarwal, Los Altos, CA (US);

Guenter Stenz, Longmont, CO (US);

Srinivasan Dasasathyan, Sunnyvale, CA (US);

Inventors:

Victor Slonim, Broomfield, CO (US);

Rajat Aggarwal, Los Altos, CA (US);

Guenter Stenz, Longmont, CO (US);

Srinivasan Dasasathyan, Sunnyvale, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.


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