The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2013

Filed:

May. 11, 2010
Applicants:

Marvin Tom, Mt. View, CA (US);

Rajat Aggarwal, Los Altos, CA (US);

Srinivasan Dasasathyan, Sunnyvale, CA (US);

Inventors:

Marvin Tom, Mt. View, CA (US);

Rajat Aggarwal, Los Altos, CA (US);

Srinivasan Dasasathyan, Sunnyvale, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/5077 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of the plurality of dies at least partially superimposed with respect to one another. The method also can include assigning, by a processor, components of the netlist to hardware units within each of the plurality of dies according, at least in part, to a wire-length metric calculated using the superimposition model.


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