The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Jul. 22, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Veeresh Pratap Singh, Hyderabad, IN;

Meghraj Kalase, Hyderabad, IN;

John Blaine, Weybridge, GB;

Srinivasan Dasasathyan, Secunderabad, IN;

Padmini Gopalakrishnan, Hyderabad, IN;

Frederic Revenu, San Carlos, CA (US);

Veena Johar, Hyderabad, IN;

Pawan Kumar Singh, Lucknow, IN;

Mohit Sharma, Jaipur, IN;

Kameshwar Chandrasekar, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/327 (2020.01); G06F 30/31 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/31 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01);
Abstract

Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.


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