The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Apr. 29, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Srinivasan Dasasathyan, Secunderabad, IN;

Padmini Gopalakrishnan, Hyderabad, IN;

Vishal Tripathy, Chandanagar, IN;

Vikas N. Vedamurthy, Hyderabad, IN;

Sumit Nagpal, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 111/04 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 2111/04 (2020.01);
Abstract

Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).


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