Xilinx, Inc.

Srinivasan Dasasathyan

Guenter Stenz

Sudip K Nag

Rajat Aggarwal

Padmini Gopalakrishnan

Marvin Tom

Wei Mark Fang

Jason Helge Anderson

Qiang Wang

Sumit Nagpal

Frederic Revenu

James L Saunders

Vishal Suthar

Hasan Arslan

Meghraj Kalase

John Blaine

Veeresh Pratap Singh

Sridhar Krishnamurthy

Anirban Rahut

Nagaraj Narasimh Savithri

Sankaranarayanan Srinivasan

Aman Gayasen

Victor Slonim

Sanjeev Kwatra

Kameshwar Chandrasekar

Anup Hosangadi

Mohit Sharma

Satish Bachina

Pavanish Nirula

Pawan Kumar Singh

Vishal Tripathy

Veena Johar

Vikas N Vedamurthy

Geetesh More

Shail Bains

Meng Lou

Gaurav Dutt Sharma

Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.

Automated timing closure on circuit designs

Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.

Visualization of data buses in circuit designs

Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).

Automated analysis and optimization of circuit designs

Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.

System and method for an electronic design tool providing automated guidance and interface for circuit design processing

A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.

Testing critical paths of a circuit design

A method of partitioning a circuit design can include identifying a circuit design in which components of the circuit design are assigned to each of a plurality of regions, wherein each region corresponds to a physical portion of an integrated circuit. A maximum oversubscription region can be determined for a selected component type from the plurality of regions. A target region from the plurality of regions can be selected that is adjacent to the region of maximum oversubscription. The method also can include re-assigning, by a processor, a selected number of components of the maximum oversubscription region to the target region.

Multi-resource aware partitioning for integrated circuits

A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.

Implementing sub-circuits with predictable behavior within a circuit design

A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of the plurality of dies at least partially superimposed with respect to one another. The method also can include assigning, by a processor, components of the netlist to hardware units within each of the plurality of dies according, at least in part, to a wire-length metric calculated using the superimposition model.

Routability based placement for multi-die integrated circuits

A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.

Method of placing input/output blocks on an integrated circuit device

A computer-implemented method of globally placing a circuit design on a programmable integrated circuit (IC) includes dividing, by a placement system, the programmable IC into a grid comprising a plurality of cells, assigning each component of a selected component type of the circuit design to one of a plurality of control set groups according to a control set of the component, and calculating a force including a control set force that depends upon overlap of control sets within the plurality of cells. The method further can include applying the force to at least one selected component of the circuit design and assigning components of the circuit design to locations on the programmable IC by solving a set of linear equations that depend upon application of the force to the at least one selected component to create a global placement. The circuit design including the global placement can be output.

Control set constraint driven force directed analytical placer for programmable integrated circuits

A method of placing clock circuits in an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the integrated circuit; identifying portions of the circuit design comprising clock circuits; determining an order of clock circuits to be placed based upon resource requirements of the clock circuits; and placing the portions of the circuit design comprising clock circuits in sites of the integrated circuit. A system for placing clock circuits in an integrated circuit is also disclosed.

Method of and system for placing clock circuits in an integrated circuit

A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC. The method can include storing an objective function and determining a result indicating whether a feasible solution exists for clock domain partitioning of the circuit design by minimizing the objective function subject to the plurality of constraints. The result can be output.

Clock domain partitioning of programmable integrated circuits

Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.

Methods of estimating net delays in tile-based PLD architectures

A method of placing a circuit design can include selecting one or more candidate mobile nodes from a plurality of overlapped nodes of the circuit design and determining a gain region for each candidate mobile node. The method also can include assigning the candidate mobile node to a site within a gain region according to a cost function. The gain region is associated with the candidate mobile node. The method further can include iteratively selecting and assigning candidate mobile nodes according to a measure of overlap for the circuit design.

Cost-based performance driven legalization technique for placement in logic designs

Approaches for placing a plurality of input/output blocks (IOBs) of an electronic design in an integrated circuit are disclosed. The electronic design includes at least one input/output bus associated with a plurality of the IOBs, and the IOBs for each input/output bus are assigned to respective sets. For each combination of pairs of the sets a respective weight factor is generated to indicate a degree of coupling between the first and second sets in the electronic design. An order of the sets is generated, and the sets are placed in an ordered series of input/output sites in the integrated circuit according to the order of the sets. A cost function is evaluated for the pairs of the sets. The generating of the order of the sets and the placing of the sets is conditionally repeated responsive to the evaluating of the cost function.

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Sunnyvale, CA, United States of America

Srinivasan Dasasathyan