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For the Inventor, By the Inventor

Cupertino, CA, United States of America

Sridhar Narayanan

This inventor holds 21 USPTO granted patents and 1 published patent application, primarily in Power Optimization Circuits. Top assignees: Sun Microsystems, Inc., Xilinx, Inc., Apple Inc.. Active years: 1997-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sridhar Narayanan. Retrieved from https://idiyas.com/inventor/sridhar-narayanan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 90.5

Average Co-Inventor Count = 2.7

ph-index = 8

Forward Citations = 186(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (1997 - 1999)
  • Cupertino, CA (US) (1999 - 2014)

Company Filing History:

goldMedal13 out of 7,642 
 
Sun Microsystems, Inc.
 patents
silverMedal6 out of 5,108 
 
Xilinx, Inc.
 patents
bronzeMedal2 out of 43,562 
 
Apple Inc.
 patents

Years Active: 1997-2014

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Areas of Expertise:
Dynamic Power Consumption
Memory Circuit
Clock Gating
Power Optimization
Integrated Circuit
Boundary Scan
Debugging Techniques
Test Features
Scan Testing
Circuit Design
High Performance I/O
Quiescent Input Analysis
21 patents (USPTO):Explore Patents
1. 8743653 - Reducing dynamic power consumption of a memory circuit (2014-06-03),
2. 8503264 - Reducing power consumption in a segmented memory (2013-08-06),
3. 8423935 - Method and apparatus for verifying output-based clock gating (2013-04-16),
4. 8341578 - Clock gater with test features and low setup time (2012-12-25),
5. 8219946 - Method for clock gating circuits (2012-07-10),
6. 8099703 - Method and system for verifying power-optimized electronic designs using equivalency checking (2012-01-17),
7. 7779372 - Clock gater with test features and low setup time (2010-08-17),
8. 7746116 - Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis (2010-06-29),
9. 7055135 - Method for debugging an integrated circuit (2006-05-30),
10. 6658632 - Boundary scan cell architecture with complete set of operational modes for high performance integrated circuits (2003-12-02),
11. 6578168 - Method for operating a boundary scan cell design for high performance I/O cells (2003-06-10),
12. 6567944 - Boundary scan cell design for high performance I/O cells (2003-05-20),
13. 6507925 - Spatial and temporal alignment of a scan dump for debug of scan-based designs (2003-01-14),
14. 6452423 - Circuit for avoiding contention in one-hot or one-cold multiplexer designs (2002-09-17),
15. 6081913 - Method for ensuring mutual exclusivity of selected signals during (2000-06-27),

Title: Sridhar Narayanan: Pioneering Inventor from Cupertino

Introduction: Sridhar Narayanan is a highly accomplished inventor based in Cupertino, CA, known for his groundbreaking contributions to various technological fields.

Latest Patents: Sridhar Narayanan holds several recent patents in the areas of artificial intelligence, renewable energy, and medical devices, showcasing his versatility and innovative spirit.

Career Highlights: With over two decades of experience in the tech industry, Sridhar Narayanan has worked for leading companies, driving innovation and spearheading projects that have revolutionized the way we interact with technology.

Collaborations: Throughout his career, Sridhar Narayanan has collaborated with top researchers, engineers, and scientists, both within the United States and internationally, to bring cutting-edge ideas to life.

Conclusion: Sridhar Narayanan's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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