The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2010
Filed:
Jan. 21, 2009
Sridhar Narayanan, Cupertino, CA (US);
Chaiyasit Manovit, Mountain View, CA (US);
Sridhar Subramanian, Cupertino, CA (US);
Gerald Gras, Palo Alto, CA (US);
Sridhar Narayanan, Cupertino, CA (US);
Chaiyasit Manovit, Mountain View, CA (US);
Sridhar Subramanian, Cupertino, CA (US);
Gerald Gras, Palo Alto, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element, wherein the first clock enable signal is generated to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.