The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2000

Filed:

Jun. 03, 1997
Applicant:
Inventors:

Sridhar Narayanan, Cupertino, CA (US);

Marc E Levitt, Sunnyvale, CA (US);

Assignee:

Sun Microsystems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
714724 ; 714727 ; 714731 ; 714744 ;
Abstract

A method for controlling a gating circuit of an electronic system incorporating a scan architecture complying with IEEE Standard 1149.1 such that the gating circuit applies mutually exclusive signals to, for example, a decoded multiplexer. The gating circuit receives input signals from flip-flops that are part of a scan chain, is selectively controllable by a control signal to transmit predetermined mutually exclusive signals to the select inputs of the multiplexer during a scan mode. Alternatively, the gating circuit is controllable by the control signal to pass the input signals to the multiplexer in a normal operation or test mode. A mutual exclusivity circuit is provided to generate the control signal. During the scan mode, the control signal is generated at a first logic level such that the gating circuit transmits the predetermined mutually exclusive signals to the multiplexer while test values are being scanned into the flip-flops. Upon transition from the scan mode to the normal operation mode, the control signal is changed to a second logic level for a predetermined time period, and then changed back to the first logic level. When the control signal is at the second logic level, the gating circuit passes the input signals to the multiplexer, and the electronic system operates to propagate response signals that are applied to, for example, the scan chain flip-flops. In some instances, these response signals received by the flip-flops are not mutually exclusive, and the multiplexer may be damaged. The predetermined time period is set to apply the predetermined mutually exclusive signals before this possible damage occurs.


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