The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2003

Filed:

Jul. 14, 2000
Applicant:
Inventors:

Gajendra P. Singh, Sunnyvale, CA (US);

Jaya Prakash Samala, San Jose, CA (US);

Sridhar Narayanan, Cupertino, CA (US);

Ishwardutt Parulkar, San Francisco, CA (US);

Assignee:

Sun Microsystems, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract

A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.


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