The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Feb. 25, 2011
Chaiyasit Manovit, Bangkok, TH;
Sridhar Narayanan, Cupertino, CA (US);
Wanlin Cao, Sunnyvale, CA (US);
Sridhar Subramanian, Cupertino, CA (US);
Alok Kuchlous, Bangalore, IN;
Chaiyasit Manovit, Bangkok, TH;
Sridhar Narayanan, Cupertino, CA (US);
Wanlin Cao, Sunnyvale, CA (US);
Sridhar Subramanian, Cupertino, CA (US);
Alok Kuchlous, Bangalore, IN;
Xilinx, Inc., San Jose, CA (US);
Abstract
One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.