The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2012
Filed:
Jul. 13, 2010
Chaiyasit Manovit, Mt. View, CA (US);
Wanlin Cao, Sunnyvale, CA (US);
Sridhar Narayanan, Cupertino, CA (US);
Sridhar Subramanian, Cupertino, CA (US);
Chaiyasit Manovit, Mt. View, CA (US);
Wanlin Cao, Sunnyvale, CA (US);
Sridhar Narayanan, Cupertino, CA (US);
Sridhar Subramanian, Cupertino, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In one embodiment, a method is provided for generating clock gating circuitry for a circuit design model. A Boolean expression of path sensitization is determined for each gate element in the netlist of a circuit design. For each gate element, a conjunction of the Boolean expression of the path sensitization and a Boolean expression of a disjunction of the observability conditions of one or more subsequent gates is determined to produce an intermediate Boolean expression. Intermediate Boolean expressions are backward retimed to produce the respective Boolean expression of the observability conditions of the each gate element. Clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements are generated and incorporated into the circuit design model.