The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2014
Filed:
Jun. 20, 2012
Sridhar Narayanan, Cupertino, CA (US);
Sridhar Subramanian, Cupertino, CA (US);
Subodh Kumar, San Jose, CA (US);
Matthew H. Klein, San Jose, CA (US);
Sridhar Narayanan, Cupertino, CA (US);
Sridhar Subramanian, Cupertino, CA (US);
Subodh Kumar, San Jose, CA (US);
Matthew H. Klein, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.