The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2003

Filed:

Jun. 15, 2000
Applicant:
Inventors:

Ishwardutt Parulkar, San Francisco, CA (US);

Sridhar Narayanan, Cupertino, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

An electrical circuit includes a flip-flop, a first multiplexer, a second flip-flop, a third flip-flop, and output storage element including a second multiplexer and a fourth flip-flop. The first flip-flop, clocked functional clock signal, receives a functional signal. The first multiplexer receives the output of the first flip-flop and a test mode shift-in signal, and outputs one of them based on the state of a select input. The second flip-flop, clocked by a test clock signal, receives the output of the first multiplexer. The third flip-flop, clocked by a second test clock signal, receives the output of the second flip-flop. The second multiplexer receives the functional signal and the output of the third flip-flop, and outputs one of them based on a mode select input signal. The fourth flip-flop, clocked by a pulse-controlled functional clock signal, receives the output of the second multiplexer.


Find Patent Forward Citations

Loading…