Sun Microsystems, Inc.

Xilinx, Inc.

Apple Inc.

Sridhar Narayanan

Sridhar Subramanian

Chaiyasit Manovit

Ishwardutt Parulkar

Marc E Levitt

Pradeep R Trivedi

Edgardo F Klass

Brian J Campbell

Matthew H Klein

Gajendra Prasad Singh

Shaishav A Desai

Jaya Prakash Samala

Ashutosh K Das

Wanlin Cao

Patrick J Crotty

Amitava Majumdar

Amit D Sanghani

Hong Seok Kim

Subodh Kumar

Paul J Dickinson

Alok Kuchlous

Yuncheng F Yu

Arthur Lin

Amit Majumdar

Cary Chin

Gregory S Clausen

Hongyu Li

Gerald Gras

A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.

Reducing dynamic power consumption of a memory circuit

A memory structure can include a first memory block including a plurality of memory cells corresponding to a first subset of addresses of a range of addresses and a second memory block including a plurality of memory cells corresponding to a second subset of addresses of the range of addresses. The memory structure can include control circuitry coupled to the first memory block and the second memory block and configured to provide control signals to the first memory block and the second memory block. The first memory block and the second memory block can be configured to implement a reduced power mode independently of one another responsive to the control signals.

Reducing power consumption in a segmented memory

One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.

Method and apparatus for verifying output-based clock gating

A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit. The delay circuit comprises at least one inverter, wherein an input of the delay circuit is the clock input, and wherein a first inverter of the delay circuit is coupled to receive a test input signal and is configured to force a first logical state on an output of the first inverter responsive to an assertion of the test input signal.

Clock gater with test features and low setup time

In one embodiment, a method is provided for generating clock gating circuitry for a circuit design model. A Boolean expression of path sensitization is determined for each gate element in the netlist of a circuit design. For each gate element, a conjunction of the Boolean expression of the path sensitization and a Boolean expression of a disjunction of the observability conditions of one or more subsequent gates is determined to produce an intermediate Boolean expression. Intermediate Boolean expressions are backward retimed to produce the respective Boolean expression of the observability conditions of the each gate element. Clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements are generated and incorporated into the circuit design model.

Method for clock gating circuits

Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent limitations which make combinational equivalency checkers unable to prove equivalency of the two designs in a single step, a series of intermediate design transformations is introduced. These transformations are dependent on the techniques used in generating the power optimized design from the golden design, and may be generically described in a transformation language that provides the necessary constructs to specify an entire set of valid structural modifications. The equivalency between the golden design and the power optimized design can then be verified by checking the golden design and the first design transformation, and then by checking between each pair of the plurality of intermediate design transformations, and finally by checking the last design transformation and the power optimized design.

Method and system for verifying power-optimized electronic designs using equivalency checking

One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element, wherein the first clock enable signal is generated to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.

Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis

Embodiments of the present invention provide a method and apparatus for debugging an integrated circuit. In particular, one embodiment of the present invention includes steps of: (a) retrieving data from a design data base, and creating a design pattern in a pattern format, which design pattern includes stimulus data for stimuli to be applied to the integrated circuit and design response data for expected responses to the stimuli; (b) generating, responsive to the design pattern, a tester pattern and a test program for input to a tester; (c) testing the integrated circuit in the tester, responsive to the tester pattern and the test program, and generating a datalog that comprises test response data; and (d) generating a file, responsive to the datalog, wherein the test response data are reformatted into the pattern format.

Method for debugging an integrated circuit

An electrical circuit includes a flip-flop, a first multiplexer, a second flip-flop, a third flip-flop, and output storage element including a second multiplexer and a fourth flip-flop. The first flip-flop, clocked functional clock signal, receives a functional signal. The first multiplexer receives the output of the first flip-flop and a test mode shift-in signal, and outputs one of them based on the state of a select input. The second flip-flop, clocked by a test clock signal, receives the output of the first multiplexer. The third flip-flop, clocked by a second test clock signal, receives the output of the second flip-flop. The second multiplexer receives the functional signal and the output of the third flip-flop, and outputs one of them based on a mode select input signal. The fourth flip-flop, clocked by a pulse-controlled functional clock signal, receives the output of the second multiplexer.

Boundary scan cell architecture with complete set of operational modes for high performance integrated circuits

A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.

Method for operating a boundary scan cell design for high performance I/O cells

Boundary scan cell design for high performance I/O cells

A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to before an event. The third value corresponds to after an event and may be incremented with ongoing clock cycles.

Spatial and temporal alignment of a scan dump for debug of scan-based designs

A circuit for avoiding contention in such circuits as an n-to-1 transmission gate multiplexer in a high performance microprocessor or integrated circuit utilizes a same-gate symmetrical design and reverse polarity control signals to overcome disadvantages of prior circuits while accommodating increasing circuit speeds. The circuit employs all NAND gates on the select lines controlling multiplexer transmission gates rather than NAND gates and a NOR gate. The design may also be implemented using AND gates. In addition to using a NAND gate where prior designs use a NOR gate, the polarity of the flip-flop output which drives the additional NAND gate is inverted, and the polarity of the input to the transmission gate driven by the additional NAND gate is also inverted. The circuit thus provides a symmetric design using the same NAND logic gates on all select lines while preserving functionality of the n-to-1 multiplexer. The symmetry of the design avoids problems which are inherent to prior asymmetrical designs is having NAND gates and a NOR gate, such as uneven delays on the select lines which can result in a short circuit for brief periods of time and the additional design effort required to overcome loading on NOR gate inputs resulting from NOR gates having increased area.

Circuit for avoiding contention in one-hot or one-cold multiplexer designs

A method for controlling a gating circuit of an electronic system incorporating a scan architecture complying with IEEE Standard 1149.1 such that the gating circuit applies mutually exclusive signals to, for example, a decoded multiplexer. The gating circuit receives input signals from flip-flops that are part of a scan chain, is selectively controllable by a control signal to transmit predetermined mutually exclusive signals to the select inputs of the multiplexer during a scan mode. Alternatively, the gating circuit is controllable by the control signal to pass the input signals to the multiplexer in a normal operation or test mode. A mutual exclusivity circuit is provided to generate the control signal. During the scan mode, the control signal is generated at a first logic level such that the gating circuit transmits the predetermined mutually exclusive signals to the multiplexer while test values are being scanned into the flip-flops. Upon transition from the scan mode to the normal operation mode, the control signal is changed to a second logic level for a predetermined time period, and then changed back to the first logic level. When the control signal is at the second logic level, the gating circuit passes the input signals to the multiplexer, and the electronic system operates to propagate response signals that are applied to, for example, the scan chain flip-flops. In some instances, these response signals received by the flip-flops are not mutually exclusive, and the multiplexer may be damaged. The predetermined time period is set to apply the predetermined mutually exclusive signals before this possible damage occurs.

Growing community of inventors

Cupertino, CA, United States of America

Sridhar Narayanan