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For the Inventor, By the Inventor

Taipei, Taiwan

Shuo-Mao Chen

This inventor holds 128 USPTO granted patents and 12 published patent applications, primarily in Semiconductor Packaging (CPC class H01L23-3128). Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2005-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shuo-Mao Chen. Retrieved from https://idiyas.com/inventor/shuo-mao-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 128 

% Patents Active = 96.9

Average Co-Inventor Count = 4.0

ph-index = 11

Forward Citations = 2,609(Granted Patents)

Forward Citations (Not Self Cited) = 2,419(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Hsin-Chuang, TW (2012 - 2013)
  • Hsin-Chu, TW (2005 - 2023)
  • New Taipei, TW (2014 - 2024)

Company Filing History:

goldMedal128 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2005-2026

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Areas of Expertise:
Chip Package Structure
Semiconductor Package
Integrated Circuit
Photonics Integrated Circuit
Multi-Chip Packages
Thermal Dissipation
Redistribution Layer
Integrated Passive Devices
Cavity Formation
Hybrid Interposer
Reinforcing Package
Manufacturing Method
128 patents (USPTO):Explore Patents
1. 12550792 - Semiconductor package and method of manufacturing the same (2026-02-10),
2. 12550757 - Chip package structure (2026-02-10),
3. 12506008 - Package structure (2025-12-23),
4. 12500158 - Semiconductor structure and manufacturing method thereof (2025-12-16),
5. 12494436 - Integrated passive device dies and methods of forming and placement of the same (2025-12-09),
6. 12476223 - Semiconductor package and method of manufacturing the same (2025-11-18),
7. 12444663 - Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof (2025-10-14),
8. 12381180 - Multi-chip packages and methods of forming the same (2025-08-05),
9. 12368142 - Double side integration semiconductor package and method of forming the same (2025-07-22),
10. 12355001 - Semiconductor package structure and method for forming the same (2025-07-08),
11. 12354940 - Redistribution layer structure with support features and methods (2025-07-08),
12. 12322742 - Semiconductor structure and manufacturing method thereof (2025-06-03),
13. 12293974 - Photonics integrated circuit package (2025-05-06),
14. 12293141 - Integrated circuit stack verification method and system for performing the same (2025-05-06),
15. 12272629 - Semiconductor device having an integrated device positioned within a hybrid interposer that includes organic and non-organic materials (2025-04-08),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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