The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

May. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Monsen Liu, Hsinchu, TW;

Shang-Lun Tsai, Hsinchu, TW;

Shuo-Mao Chen, New Taipei, TW;

Shin-Puu Jeng, Po-Shan Village, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/162 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 25/167 (2013.01); H01L 21/4853 (2013.01); H01L 25/165 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/16152 (2013.01); H01L 2924/16251 (2013.01); H01L 2924/182 (2013.01); H01L 2924/183 (2013.01);
Abstract

An embodiment semiconductor device includes a first die package component, a second interposer electrically coupled to a first side of the first die package component, a third interposer having a voltage regulator circuit electrically coupled to a second side of the first die package component, and an optical component and a high-bandwidth-memory die, each electrically coupled to the second interposer. The first die package component may further include a double-sided semiconductor die, such that a first side of the double-sided semiconductor die is electrically coupled to the second interposer, and a second side of the double-sided semiconductor die is electrically coupled to the third interposer. The first die package component may further include a molding material and a through-molding-via formed in the molding material, such that the through-molding-via provides an electrical connection between the second interposer and the third interposer that bypasses the double-sided semiconductor die.


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