Taiwan Semiconductor Manufacturing Comp. Ltd.

Shuo-Mao Chen

Shin-Puu Jeng

Feng-Cheng Hsu

Der-Chyang Yeh

Po-Yao Lin

Jui-Pin Hung

Po-Yao Chuang

Chiung-Han Yeh

Po-Hao Tsai

Chewn-Pu Jou

Feng Wei Kuo

Hsien-Wen Liu

Yi-Jou Lin

Cheng-Yi Hong

Jing-Cheng Lin

Ming-Chih Yew

Techi Wong

Li-Hsien Huang

Hsiao-Wen Lee

Chia-Kuei Hsu

Chih-Hsien Lin

Monsen Liu

Han-Hsiang Huang

Chia-Hsiang Lin

Shang-Lun Tsai

Shu-Shen Yeh

Mill-Jer Wang

Ho-Hsiang Chen

Chen-Hua Lin

Chao-Hsiang Yang

Kuang-Chun Lee

Dai-Jang Chen

Chin-Yuan Huang

Kai-Yun Lin

Shang-Yun Hou

Chin-Hua Wang

Chih-Ping Chao

Meng-Liang Lin

Yu-Ting Huang

Hsiang-Tai Lu

De-Dui Liao

Te-Chi Wong

Chen-Hua Douglas Yu

Huan-Neng Chen

Chih-Sheng Chang

Po-Hsiang Huang

Fong-yuan Chang

Meng-Wei Chou

Yu-Hao Chen

Jyh Chwen Frank Lee

Ching-Yi Lin

Po-Ying Lai

Arunima Banerjee

Jaw-Juinn Horng

Chung-Hui Chen

Chia-Chung Chen

Chin-Chou Liu

Jui-Feng Kuan

Chin-Wei Kuo

Jun-De Jin

Hua-Chou Tseng

Sally Liu

Sung-Hsiung Wang

Heng-Ming Hsu

Hsiang-tai Lu

Yen-Chu Tu

Christianto Chih-Ching Liu

Provided is a package structure including a die, a through via, an encapsulant, a warpage controlling layer, and a cap. The through via is laterally aside the die. The encapsulant laterally encapsulates the through via and the die. The warpage controlling layer covers the encapsulant and the die. The cap is laterally aside the warpage controlling layer and on the through via. The cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the warpage controlling layer.

Package structure

A method includes: forming a first interposer die, wherein the first interposer die comprises a first substrate and a first redistribution layer (RDL) over the first substrate; bonding the first interposer die to a second RDL; encapsulating the second RDL and the first interposer die with a first encapsulating layer; thinning the first interpose die to expose the first RDL; and bonding a first semiconductor die to the first RDL.

Semiconductor structure and manufacturing method thereof

A method of fabricating integrated passive device dies includes forming a first plurality of integrated passive devices on a substrate, forming a plurality of micro-bumps on the first plurality of integrated passive devices such that the plurality of micro-bumps act as electrical connections to the integrated passive devices, and dicing the substrate to form an integrated passive device die including a second plurality of integrated passive devices. The micro-bumps may be formed in an array or staggered configuration and may have a pitch that is in a range from 20 microns to 100 microns. The integrated passive devices may each include a seal ring and the integrated passive device die may have an area that is a multiple of an integrated passive device area. The method may further include dicing the substrate in various ways to generate integrated passive device dies having different sizes and numbers of integrated passive devices.

Integrated passive device dies and methods of forming and placement of the same

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

Semiconductor package and method of manufacturing the same

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof

Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Multi-chip packages and methods of forming the same

An embodiment semiconductor device includes a first die package component, a second interposer electrically coupled to a first side of the first die package component, a third interposer having a voltage regulator circuit electrically coupled to a second side of the first die package component, and an optical component and a high-bandwidth-memory die, each electrically coupled to the second interposer. The first die package component may further include a double-sided semiconductor die, such that a first side of the double-sided semiconductor die is electrically coupled to the second interposer, and a second side of the double-sided semiconductor die is electrically coupled to the third interposer. The first die package component may further include a molding material and a through-molding-via formed in the molding material, such that the through-molding-via provides an electrical connection between the second interposer and the third interposer that bypasses the double-sided semiconductor die.

Double side integration semiconductor package and method of forming the same

A device includes a semiconductor chip and a redistribution layer (RDL) structure connected to the semiconductor chip. The redistribution layer structure comprises a first region including: a first bump connected to the semiconductor chip; a second bump; and a plurality of first redistribution layers connected between the first bump and the second bump. The RDL structure includes a second region laterally surrounding the first region, the second region including a plurality of second redistribution layers. The RDL structure includes an isolation region laterally separating the plurality of first redistribution layers from the plurality of second redistribution layer. The isolation region includes at least one region that is straight, continuous, extends from an upper surface of the redistribution layer structure to a lower surface of the first redistribution layer structure, and has at least a selected width.

Redistribution layer structure with support features and methods

A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a connecting element, a first semiconductor device, a second semiconductor device, a first underfill layer, and a package layer. The interposer substrate is disposed on the carrier substrate. The connecting element is disposed in the interposer substrate. The connecting element includes a dielectric element and first conductive features disposed in the dielectric element. The first semiconductor device and the second semiconductor device are disposed on the interposer substrate. The first semiconductor device is electrically connected to the second semiconductor device through the connecting element. The first underfill layer is disposed between the first semiconductor device, the second semiconductor device, and the interposer substrate. The package layer surrounds the first semiconductor device, the second semiconductor device, and the first underfill layer.

Semiconductor package structure and method for forming the same

A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.

A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Integrated circuit stack verification method and system for performing the same

An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Photonics integrated circuit package

Devices and methods of manufacture for a hybrid interposer within a semiconductor device. A semiconductor device may include a package substrate and a hybrid interposer. The hybrid interposer may include an organic interposer material layer, and a non-organic interposer material layer positioned between the organic interposer material layer and the package substrate. The semiconductor device may further include an integrated device positioned within the hybrid interposer. In one embodiment, the integrated device may be positioned within the organic interposer material layer. In another embodiment, the integrated device may be positioned within the non-organic interposer material layer. In a further embodiment, the integrated device may be positioned within the organic interposer material layer and the non-organic interposer material layer.

Semiconductor device having an integrated device positioned within a hybrid interposer that includes organic and non-organic materials

A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.

Package structure with lid and method for forming the same

An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

Semiconductor packages including passive devices and methods of forming same

Growing community of inventors

Taipei, Taiwan

Shuo-Mao Chen