The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Apr. 19, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Shang-Lun Tsai, Hsinchu, TW;

Shuo-Mao Chen, New Taipei, TW;

Po-Ying Lai, Hsinchu, TW;

Monsen Liu, Hsinchu, TW;

Shin-Puu Jeng, Po-Shan Village, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/495 (2006.01); H10D 84/01 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 23/147 (2013.01); H01L 23/49579 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H10D 84/01 (2025.01); H01L 2224/16012 (2013.01); H01L 2224/32106 (2013.01); H01L 2224/73204 (2013.01);
Abstract

A method of fabricating integrated passive device dies includes forming a first plurality of integrated passive devices on a substrate, forming a plurality of micro-bumps on the first plurality of integrated passive devices such that the plurality of micro-bumps act as electrical connections to the integrated passive devices, and dicing the substrate to form an integrated passive device die including a second plurality of integrated passive devices. The micro-bumps may be formed in an array or staggered configuration and may have a pitch that is in a range from 20 microns to 100 microns. The integrated passive devices may each include a seal ring and the integrated passive device die may have an area that is a multiple of an integrated passive device area. The method may further include dicing the substrate in various ways to generate integrated passive device dies having different sizes and numbers of integrated passive devices.


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