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Yokohama, Japan

Shunsuke Kodera

This inventor holds 16 USPTO granted patents. Top assignees: Toshiba Memory Corporation, Kabushiki Kaisha Toshiba. Active years: 2017-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shunsuke Kodera. Retrieved from https://idiyas.com/inventor/shunsuke-kodera

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16

% Patents Active = 100.0

Average Co-Inventor Count = 4.6

ph-index = 2

Forward Citations = 18(Granted Patents)

Location History:

Yokohama, JP (2019)
Kanagawa, JP (2017 - 2020)
Yokohama Kanagawa, JP (2017 - 2020)

Company Filing History:

13 out of 2,955

Toshiba Memory Corporation

3 out of 53,262

Kabushiki Kaisha Toshiba

Years Active: 2017-2020

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16 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10769011 - Memory device that changes a writable region of a data buffer based on an operational state of an ECC circuit (2020-09-08),

2. 10732863 - Memory system storing block protection information (2020-08-04),

3. 10621034 - Memory device that changes a writable region of a data buffer based on an operational state of an ECC circuit (2020-04-14),

4. 10489088 - Storage device compatible with selected one of multiple interface standards (2019-11-26),

5. 10452474 - NAND flash memory device (2019-10-22),

6. 10445174 - Memory device that communicates error correction results to a host (2019-10-15),

7. 10353852 - Memory system that stores data redundantly (2019-07-16),

8. 10310755 - Memory system having a semiconductor memory device with protected blocks (2019-06-04),

9. 10289482 - Memory device that updates parameters transmitted to a host based on operational settings (2019-05-14),

10. 10235306 - Storage device compatible with selected one of multiple interface standards (2019-03-19),

11. 10235070 - Memory system having a semiconductor memory device with protected blocks (2019-03-19),

12. 9959937 - Memory system including test circuit (2018-05-01),

13. 9891987 - Memory device that communicates error correction results to a host (2018-02-13),

14. 9747994 - Memory system (2017-08-29),

15. 9728275 - Memory system that handles access to bad blocks (2017-08-08),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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