The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Mar. 04, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shunsuke Kodera, Yokohama Kanagawa, JP;

Toshihiko Kitazume, Kawasaki Kanagawa, JP;

Kenichirou Kada, Yokohama Kanagawa, JP;

Nobuhiro Tsuji, Yokohama Kanagawa, JP;

Shinya Takeda, Yokohama Kanagawa, JP;

Tetsuya Iwata, Yokohama Kanagawa, JP;

Yoshio Furuyama, Yokosuka Kanagawa, JP;

Hirosuke Narai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1044 (2013.01); G06F 11/1052 (2013.01); G06F 11/1068 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.


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