The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2017
Filed:
Aug. 10, 2016
Kabushiki Kaisha Toshiba, Tokyo, JP;
Hirosuke Narai, Tokyo, JP;
Toshihiko Kitazume, Kanagawa, JP;
Kenichirou Kada, Kanagawa, JP;
Nobuhiro Tsuji, Kanagawa, JP;
Shunsuke Kodera, Kanagawa, JP;
Tetsuya Iwata, Kanagawa, JP;
Yoshio Furuyama, Kanagawa, JP;
Shinya Takeda, Kanagawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays. The interface circuit and the first and second memory cell arrays are provided in one common package, and is configured to access the first memory cell array when detecting the first chip select signal, and to access the second memory cell array when detecting the second chip select signal.