The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Feb. 22, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shunsuke Kodera, Yokohama Kanagawa, JP;

Kenichirou Kada, Yokohama Kanagawa, JP;

Shinya Takeda, Yokohama Kanagawa, JP;

Kiyotaka Hayashi, Kawasaki Kanagawa, JP;

Yoshio Furuyama, Yokosuka Kanagawa, JP;

Tetsuya Iwata, Yokohama Kanagawa, JP;

Wangying Lin, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/24 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0622 (2013.01); G06F 3/064 (2013.01); G06F 3/0637 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/1425 (2013.01); G06F 13/16 (2013.01); G11C 7/24 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/214 (2013.01); G06F 2212/7207 (2013.01);
Abstract

A memory system includes a controller that recognizes, as a command, a signal received immediately after a chip select signal is received from a host device, and a memory that includes a plurality of blocks. When the command is a first command, the controller outputs to the host device, information indicating whether at least one of a write operation and an erase operation with respect to at least one particular block is prohibited.


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