The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Mar. 04, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Kenichirou Kada, Yokohama Kanagawa, JP;

Shinya Takeda, Yokohama Kanagawa, JP;

Toshihiko Kitazume, Kawasaki Kanagawa, JP;

Mikio Takasugi, Kawasaki Kanagawa, JP;

Nobuhiro Tsuji, Yokohama Kanagawa, JP;

Shunsuke Kodera, Yokohama Kanagawa, JP;

Tetsuya Iwata, Yokohama Kanagawa, JP;

Yoshio Furuyama, Yokosuka Kanagawa, JP;

Hirosuke Narai, Yokosuka Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G11C 29/44 (2006.01); G11C 29/32 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01); G11C 16/04 (2006.01); G11C 29/36 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 29/32 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01); G11C 16/0483 (2013.01); G11C 29/36 (2013.01); G11C 2207/107 (2013.01);
Abstract

A memory system includes a semiconductor memory device, a controller configured to access the semiconductor module, a plurality of pins for connection to the outside of the memory system, the pins configured to receive and output serial data, and a test circuit. When one of the pins receives serial test data, the test circuit converts the serial test data into parallel test data, and outputs the parallel test data to the semiconductor memory device for writing therein, and when the test circuit receives parallel test data written in the semiconductor memory device, the test circuit converts the parallel test data to serial test data, and outputs the serial test data through one of the pins for test of the memory system.


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