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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10235306 B1

PDFFull Text
Date of Patent:
Mar. 19, 2019

Filed:

Mar. 01, 2017

Storage device compatible with selected one of multiple interface standards

Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shunsuke Kodera, Yokohama Kanagawa, JP;

Yoshio Furuyama, Yokosuka Kanagawa, JP;

Assignee:

TOSHIBA MEMORY CORPORATION, Tokyo, JP;

Attorney:

Kim & Stewart LLP

Primary Examiner:

Brian T Misiura

Int. Cl.
CPC ...
G06F 13/10 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 13/102 (2013.01); G06F 11/1068 (2013.01); G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G11C 7/10 (2013.01); G11C 7/1075 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/102 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 29/52 (2013.01); G11C 2207/107 (2013.01);
Abstract

A storage device includes a nonvolatile semiconductor memory module, a first interface circuit, and a second interface circuit conforming to an interface standard different from an interface standard of the first interface circuit. One of the first interface circuit and the second interface circuit is connected to the nonvolatile semiconductor memory module via first wiring, and to terminals of the storage device for connection to a host via second wiring. The other one of the first interface circuit and the second interface circuit is not connected to either the nonvolatile semiconductor memory module or the terminals.

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