The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2019

Filed:

Feb. 24, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shunsuke Kodera, Yokohama Kanagawa, JP;

Toshihiko Kitazume, Kawasaki Kanagawa, JP;

Kenichirou Kada, Yokohama Kanagawa, JP;

Nobuhiro Tsuji, Yokohama Kanagawa, JP;

Shinya Takeda, Yokohama Kanagawa, JP;

Tetsuya Iwata, Yokohama Kanagawa, JP;

Yoshio Furuyama, Yokosuka Kanagawa, JP;

Hirosuke Narai, Meguro Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 16/22 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0622 (2013.01); G06F 3/064 (2013.01); G06F 3/0637 (2013.01); G06F 3/0655 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 5/066 (2013.01); G11C 7/1063 (2013.01); G11C 16/22 (2013.01);
Abstract

A memory system includes a semiconductor memory device including a plurality of blocks, and a controller configured to register a block designated in a protection command as a protected block in a storage region. When the control circuit receives from a host a command to erase the protected block or write to the protected block, the control circuit does not issue a corresponding erase or write command to the semiconductor memory device and notifies the host of the failure to execute the command.


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