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For the Inventor, By the Inventor

Allen, TX, United States of America

Shashank Sureshchandra Ekbote

This inventor holds 41 USPTO granted patents and 3 published patent applications and 5 EPO patents, primarily in Field-Effect Transistors. Top assignees: Texas Instruments Corporation, Qualcomm Incorporated, Other. Active years: 2004-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shashank Sureshchandra Ekbote. Retrieved from https://idiyas.com/inventor/shashank-sureshchandra-ekbote

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 41 

% Patents Active = 92.7


Average Co-Inventor Count = 3.0

ph-index = 6

Forward Citations = 286(Granted Patents)


Location History:

  • Richardson, TX (US) (2005)
  • Irving, TX (US) (2004 - 2009)
  • Allen, TX (US) (2009 - 2018)
  • San Diego, CA (US) (2011 - 2020)

Company Filing History:

goldMedal32 out of 29,888 
 
Texas Instruments Corporation
 patents
silverMedal8 out of 44,897 
 
Qualcomm Incorporated
 patents
bronzeMedal1 out of 834,513 
Other
 patents

Years Active: 2004-2020

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Areas of Expertise:
Field-Effect Transistors
Integrated Circuits
Silicide Formation
FinFET
SRAM
Transistor Performance
Mechanical Stress
Semiconductor Doping
Cryogenic Implants
Gate Orientation
Differential Doping
Shallow Trench Isolation
41 patents (USPTO):Explore Patents
1. 10861852 - Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits (2020-12-08),
2. 10490558 - Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells (2019-11-26),
3. 10304957 - FinFET with reduced series total resistance (2019-05-28),
4. 10062768 - Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout (2018-08-28),
5. 10008499 - Method to form silicide and contact at embedded epitaxial facet (2018-06-26),
6. 9947765 - Dummy gate placement methodology to enhance integrated circuit performance (2018-04-17),
7. 9922971 - Integration of analog transistor (2018-03-20),
8. 9882051 - Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions (2018-01-30),
9. 9812452 - Method to form silicide and contact at embedded epitaxial facet (2017-11-07),
10. 9634138 - Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout (2017-04-25),
11. 9508601 - Method to form silicide and contact at embedded epitaxial facet (2016-11-29),
12. 9496142 - Dummy gate placement methodology to enhance integrated circuit performance (2016-11-15),
13. 9412741 - Integration of analog transistor (2016-08-09),
14. 9406769 - Silicide formation due to improved SiGe faceting (2016-08-02),
15. 9224653 - Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield (2015-12-29),

Certainly! Here is an article about inventor Shashank Sureshchandra Ekbote's dedication to innovation and his creative approach to problem-solving:

Title: Shashank Sureshchandra Ekbote: Pioneering Innovation for a Better Future

Introduction:

Shashank Sureshchandra Ekbote, based in Allen, TX (US), is a remarkable inventor whose dedication to innovation and problem-solving has earned him recognition in the field. With an impressive 41 patents to his name, his work is shaping the future of various industries and has the potential to enhance the quality of life for many.

Latest Patents:

Ekbote's latest patents showcase his ingenuity and technical expertise. One of his notable inventions includes the development of Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits. This innovation allows for the reduction of footprint size in IC chips by vertically integrating PFETs and NFETs in a 3D cell circuit structure.

Another groundbreaking patent by Ekbote focuses on reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells. By implementing innovative strategies such as utilizing multiple supply contacts and non-active gates, Ekbote's invention aims to stabilize Fins and enhance the efficiency of SRAM strap cells.

Career Highlights:

Throughout his career, Shashank Sureshchandra Ekbote has made significant contributions to leading companies in the industry. He has lent his expertise to renowned organizations such as Texas Instruments Corporation and Qualcomm Incorporated, where he has played a pivotal role in driving innovation and technological advancements.

Collaborations:

Ekbote's collaborative spirit is evident in his work with accomplished colleagues such as Youn Sung Choi and Borna J Obradovic. Together, they have worked on cutting-edge projects and research initiatives, further solidifying Ekbote's reputation as a collaborative and forward-thinking inventor.

Conclusion:

In conclusion, Shashank Sureshchandra Ekbote's innovative spirit and dedication to solving complex technological challenges make him a standout inventor in the field. His patent portfolio and contributions to various industries underscore his commitment to driving progress and shaping the future of innovation. Ekbote's creative approach to problem-solving continues to inspire and pave the way for groundbreaking advancements in the realm of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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