The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Oct. 03, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Kwan-Yong Lim, Plano, TX (US);

James Walter Blatchford, Richardson, TX (US);

Shashank S. Ekbote, Allen, TX (US);

Younsung Choi, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 23/535 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 23/535 (2013.01); H01L 29/4175 (2013.01);
Abstract

An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.


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