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For the Inventor, By the Inventor

Allen, TX, United States of America

Younsung Choi

This inventor holds 13 USPTO granted patents and 2 published patent applications and 3 EPO patents. Top assignee: Texas Instruments Corporation. Active years: 2013-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Younsung Choi. Retrieved from https://idiyas.com/inventor/younsung-choi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 13 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.3

ph-index = 2

Forward Citations = 23(Granted Patents)


Location History:

  • Allen, TX (US) (2016 - 2020)
  • Plano, TX (US) (2013 - 2022)

Company Filing History:

goldMedal13 out of 29,869 
 
Texas Instruments Corporation
 patents

Years Active: 2013-2022

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13 patents (USPTO):Explore Patents
1. 11251093 - Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow (2022-02-15),
2. 10734290 - Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow (2020-08-04),
3. 10559469 - Dual pocket approach in PFETs with embedded SI-GE source/drain (2020-02-11),
4. 10134643 - Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow (2018-11-20),
5. 10026837 - Embedded SiGe process for multi-threshold PMOS transistors (2018-07-17),
6. 10008499 - Method to form silicide and contact at embedded epitaxial facet (2018-06-26),
7. 9947765 - Dummy gate placement methodology to enhance integrated circuit performance (2018-04-17),
8. 9812452 - Method to form silicide and contact at embedded epitaxial facet (2017-11-07),
9. 9735159 - Optimized layout for relaxed and strained liner in single stress liner technology (2017-08-15),
10. 9583488 - Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow (2017-02-28),
11. 9508601 - Method to form silicide and contact at embedded epitaxial facet (2016-11-29),
12. 9496142 - Dummy gate placement methodology to enhance integrated circuit performance (2016-11-15),
13. 8438526 - Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions (2013-05-07),

Title: Innovations of Younsung Choi

Introduction

Younsung Choi is a prominent inventor based in Allen, Texas. He has made significant contributions to the field of integrated circuits, holding a total of 13 patents. His work focuses on improving CMOS performance, which is crucial for modern electronic devices.

Latest Patents

Among his latest patents is a methodology for poly gate extension design aimed at enhancing CMOS performance in dual stress liner process flows. This patent details an integrated circuit and method that incorporates dual stress liners, featuring NMOS transistors with gate overhangs of active regions that exceed the minimum design rule. Additionally, it includes PMOS transistors with gate overhangs that do not exceed the minimum design rule.

Career Highlights

Younsung Choi is currently employed at Texas Instruments Corporation, a leading company in the semiconductor industry. His innovative approaches have positioned him as a key figure in the development of advanced integrated circuit technologies.

Collaborations

He has collaborated with notable coworkers, including Shashank Sureshchandra Ekbote and Steven Lee Prins, contributing to various projects that enhance the capabilities of integrated circuits.

Conclusion

Younsung Choi's work exemplifies the spirit of innovation in the field of electronics, and his patents continue to influence the development of advanced technologies. His contributions are vital for the ongoing evolution of integrated circuit design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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