Texas Instruments Corporation

Younsung Choi

Shashank Sureshchandra Ekbote

Steven Lee Prins

James Walter Blatchford

Gregory Charles Baldwin

Kwan-Yong Lim

Greg Charles Baldwin

Deborah J Riley

Ebenezer Eshun

Oluwamuyiwa Oluwagbemiga Olubuyide

An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow

A p-type metal oxide semiconductor field effect transistor (PFET) includes a p-type silicon substrate and an n-type well formed in the p-type silicon substrate. The PFET also comprises a p-type source formed in the n-type well, a p-type drain formed in the n-type well, and dual pockets implanted in the n-type well and coupled to the source and drain. The dual pockets comprise a first pocket with first arsenic n-type dopants and a second pocket with second arsenic n-type dopants.

Dual pocket approach in PFETs with embedded SI-GE source/drain

An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.

Embedded SiGe process for multi-threshold PMOS transistors

An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Method to form silicide and contact at embedded epitaxial facet

A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.

Dummy gate placement methodology to enhance integrated circuit performance

An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors is adjusted for improved transistor performance.

Optimized layout for relaxed and strained liner in single stress liner technology

Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.

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Allen, TX, United States of America

Younsung Choi